1. Field of the Invention
The present invention relates to a signal processing circuit for video camera. More specifically, the present invention relates to a signal processing circuit which performs an image enhancement in a horizontal direction and/or a vertical direction in a video camera which utilizes a solid-state image sensing device having a large number of pixels arranged in a matrix fashion and a plurality of color filters having spectral sensitivity characteristics different from each other and being arranged for the pixels in a mosaic fashion.
2. Description of the Prior Art
In a color video camera utilizing such a kind of solid-state image sensing device, in corresponding to each of the pixels of the solid-state image sensing device, there is provided with a color filter having a specific color, i.e. one of three colors R, G and B, for example. Then, a luminance signal Y and color signals R, G and B are produced through a color separation performed by processing a signal from each of the pixels of the solid-state image sensing device corresponding to the specific color.
On the other hand, in the video camera, image enhancements in the horizontal direction and the vertical direction are performed by producing aperture signals (image enhancing signals) and by adding the aperture signals to the luminance signal Y.
In FIG. 4, a signal processing circuit for video camera having a prior art image enhancement function is shown. A CCD 1 is constructed by an image sensing portion 2 and a horizontal transfer portion 3. The CCD 1 is shown in FIG. 5 in detail. More specifically, photo-diodes 4, 4, . . . each performing a photoelectric conversion are provided with color filters of a mosaic arrangement as shown in FIG. 5. Then, the image sensing portion 2 includes such the photo-diodes 4 and vertical transfer CCDs 5, 5, . . . . each of which is driven by a 6-phase pulse from a vertical driving circuit 6. The horizontal transfer portion 3 includes dual-channel structure of first and second horizontal transfer CCDs 7 and 8 which are simultaneously driven by a horizontal driving circuit 9 in two phases so as to perform a double-speed reading, whereby signals of two horizontal lines can be obtained simultaneously.
In addition, an image sensing device including the above described CCD has been filed by the same assignee as that of the present invention as Japanese Patent Application Laying-open No. 6-225195 laid-open on Aug. 12, 1993, and therefore, a detailed description of the CCD will be omitted here.
The signals from the horizontal transfer portion 3, that is, from the first and second horizontal transfer CCDs 7 and 8 are processed by CDS (Correlation Double Sampling) circuits 10 and 11 and AGC (Automatic Gain Control) circuits 12 and 13, and then, converted into digital signals by A/D converter circuits 14 and 15.
The output signals from the CCD 1 which are converted into digital signals are applied to a selection circuit 18 directly or via 1H delay circuits 16 and 17. Each of the 1H delay circuits 16 and 17 includes a memory capable of storing the digital signal for one horizontal period (1H) of the CCD 1, and a digital signal being delayed by 1H is outputted from the memory. In addition, writing and reading to and from the 1H delay circuits 16 and 17 are performed in synchronous with the horizontal transfer in the solid-state image sensing device 1. Therefore, a timing generator 30 and a synchronization signal generator 31 are provided. The timing generator 30 outputs a clock signal which is applied to the horizontal driving circuit 9 (see FIGS. 6(A)-6(F)) and the 1H delay circuits 16 and 17. The synchronization signal generator 31 also receives the clock signal from the timing generator 30 so as to operate in synchronous with the timing generator 30, and outputs a horizontal synchronization signal HD (FIG. 6(A) or 7(A)), a vertical synchronization signal VD, the clock signal, and a field identification (ID) signal representative of an odd field or an even field.
The selection circuit 18 includes selectors 19, 20 and 21 which select digital signals for three lines out of signals for four lines according to an odd field or an even field. That is, the selectors 19, 20 and 21 are controlled based upon the field ID signal indicative of the odd field or the even field. Then, in the odd field, signals D0, D1, and D2 are selected, and in the even field, signals D1, D2 and D3 are selected. Therefore, from the selection circuit 18, signals L0, L1 and L2 for the three lines according to the odd field or the even field can be obtained.
More specifically, when the field ID signal indicates the odd field, that is, when the field ID signal is the low level (FIG. 6(F)), the selector 19 selects the digital signal D1, the selector 20 selects the digital signal D2, and the selector 21 selects the digital signal D3. That is, since the field ID signal is the low level as shown in FIG. 6(F), the selection circuit 18 outputs the digital signals D1, D2 and D3 shown in FIG. 6(D), FIG. 6(C), FIG. 6(B) as the output signals L0, L1 and L2 and digital signal D0 (FIG. 6E) is not output.
When the field ID signal indicates the even field, that is, when the field ID signal is the high level (FIG. 7(F)), the selector 19 selects the digital signal D0, the selector 20 selects the digital signal D1, and the selector 21 selects the digital signal D2. That is, at the even field, since the field ID signal becomes the high level as shown in FIG. 7(F), the selection circuit 18 outputs the digital signals D0, D1 and D2 shown in FIG. 7(E), FIG. 7(D) and FIG. 7(C) as the output signals L0, L1 and L2 abd digital signal D3 (FIG. 7(B)) is not output.
FIG. 8(A) is an illustrative view showing a relationship between an arrangement of the pixels on the CCD 1 and pixels being selected. As described above, in the odd field, the line signals D1, D2 and D3 are selected, and therefore, at odd pixels in the odd field, pixels to be processed become as shown in FIG. 8(B). Furthermore, at even pixels in the odd field, pixels to be processed become as shown in FIG. 8(C). On the other hand, in the even field, since the line signals D0, D1 and D2 are selected, at odd pixels in the even field, pixels to be processed become as shown in FIG. 8(D), and at even pixels in the even field, pixels to be processed become as shown in FIG. 8(E).
The signals L0, L1 and L2 from the selection circuit 18 are supplied to a horizontal aperture signal producing circuit 22 which is constructed by a vertical LPF (low-pass filter) and a horizontal BPF (band-pass filter) each being a digital filter, and a vertical aperture signal producing circuit 23 which is constructed by a horizontal LPF and a vertical BPF each being a digital filter. In the both aperture signal producing circuits 22 and 23, arithmetic operations shown by the following equations (1), (2), (3) and (4) are performed on the basis of the signals of the pixels shown in FIG. 9. EQU Hap=-(G11+G31)+2(2.times.G22)-(G13+G33) (1) EQU Vap=-(G11+G13)+2(2.times.G22)-(G31+G33) (2) EQU Hap=-2.times.G21+2(G12+G32)-2.times.G23 (3) EQU Vap=-2.times.G21+2(G21+G23)-2.times.G32 (4)
Through such the arithmetic operations, aperture signals are produced for a center pixel of nine pixels shown in FIG. 9. Furthermore, only the pixels of G occupying a half of the pixels are utilized in performing the arithmetic operations to produce the aperture signals.
In addition, a numeral of an upper digit of a suffix after each of letters R, G and B indicative of the colors indicates a position in the vertical direction, and a numeral of a lower digit indicates a position in the horizontal direction.
As to the odd pixels in the odd field, a horizontal aperture signal Hap and a vertical aperture signal Vap are respectively calculated according to the equations (1) and (2) on the basis of five G pixels shown in FIG. 9(A). Furthermore, as to the even pixels in the odd field, a horizontal aperture signal Hap and a vertical aperture signal Vap are respectively calculated according to the equations (3) and (4) on the basis of four G pixels shown in FIG. 9(B). In addition, a horizontal aperture signal Hap and a vertical aperture signal Vap are respectively calculated according to the equations (1) and (2) for the even pixels in the even field, and according to the equations (3) and (4) for the odd pixels in the even field.
Then, the horizontal aperture signal Hap and the vertical aperture signal Vap are added to each other by an adding circuit 24, and then, supplied to an aperture signal addition circuit 25 in which an aperture signal from the adding circuit 24 is added to the luminance signal Y after a YC separation.
In the above described prior art, since the pixels of G signals are arranged in a zig-zag fashion, a signal of a pixel in which no G signal originally exists out of the pixels necessary for the arithmetic operation of the aperture signal is to be evaluated through an interpolation. Therefore, in a case where a vertically-striped image in which a shade exists in the horizontal direction and a correlation in the vertical direction is large is taken by the video camera, for example, originally, it is preferable that only the horizontal aperture signal Hap is generated, and the vertical aperture signal Vap becomes zero; however, a vertical aperture signal is undesirably generated, and thus, there was a possibility that an image quantity is deteriorated because the aperture signal is added to a portion that no change in the luminance occurs. Especially, if an aperture signal having a high-frequency is to be produced, unevenness of the luminance in a high-frequency region occurs. Therefore, in the prior art, a high-frequency region of the aperture signal is restricted, and therefore, it was impossible to increase a sharpness of an image sufficiently.